Analog Devices VisualDSP++ 5.0 Service Manual page 148

Public Data Types and Enumerations
Table 3-6. ADI_PWR_COMMAND Available Commands (Cont'd)
Command
ADI_PWR_CMD_SET_PC133_COMPLIANCE
Commands valid only when passed to the adi_pwr_SetVoltageRegulator function.
ADI_PWR_CMD_SET_VR_VLEV
ADI_PWR_CMD_SET_VR_FREQ
ADI_PWR_CMD_SET_VR_GAIN
ADI_PWR_CMD_SET_VR_WAKE
ADI_PWR_CMD_SET_VR_PHYWE
ADI_PWR_CMD_SET_VR_CANWE
3-44
Associated Data Value
ADI_PWR_PC133_COMPLIANCE
whether the SDRAM is to comply with the
PC-133 standard. Non-compliance to the stan-
dard is required to enable the processor to return
from hibernate mode without losing the contents
of SDRAM. This value prevents SDRAM decay
during reset, enabling the contents of SDRAM to
be preserved through the hibernate reset or deep
sleep reset cycle. (This command does not apply
to all processors).
ADI_PWR_VLEV
required of the voltage regulator. See
"ADI_PWR_VLEV" on page
ADI_PWR_VR_FREQ
voltage regulator switching oscillator frequency.
Use the
ADI_PWR_FREQ_POWERDOWN
bypass the on-board voltage regulator. See
"ADI_PWR_VR_FREQ" on page
ADI_PWR_VR_GAIN
loop gain of the switching regulator loop
(see "ADI_PWR_VR_GAIN" on page
ADI_PWR_VR_WAKE
regulator is awakened from powerdown upon an
interrupt from the RTC or a low- going edge on
the pin. See
RESET#
on page 3-56.
ADI_PWR_VR_PHYWE
ing whether to enable/disable the
cessors with
PHYWE
"ADI_PWR_VR_PHYWE" on page
ADI_PWR_VR_CANWE
ing whether to enable or disable the
(for processors with CAN interface only). See
"ADI_PWR_VR_CANWE" on page
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
value specifying
value specifying the voltage level
3-53.
value specifying the required
value to
3-55.
value specifying the internal
3-55).
value specifying if the voltage
"ADI_PWR_VR_WAKE"
enumeration value indicat-
PHYWE
bit only). See
3-56.
enumeration value indicat-
CANWE
3-54.
bit (pro-
bit