Analog Devices VisualDSP++ 5.0 Service Manual page 178

EBIU API Reference
Table 4-1. Adi_ebiu_Control Return Values
Return Value
ADI_EBIU_RESULT_BAD_COMMAND
ADI_EBIU_RESULT_SUCCESS
ADI_EBIU_RESULT_NOT_INITIALIZED
ADI_EBIU_RESULT_INVALID_SDRAM_SRFS
ADI_EBIU_RESULT_INVALID_SDRAM_PUPSD
ADI_EBIU_RESULT_INVALID_SDRAM_PSM
ADI_EBIU_RESULT_INVALID_SDRAM_EBUFE
ADI_EBIU_RESULT_INVALID_SDRAM_FBBRW
ADI_EBIU_RESULT_INVALID_SDRAM_CDDBG
ADI_EBIU_RESULT_INVALID_SDRAM_EBE
ADI_EBIU_RESULT_INVALID_ASYNCH_BANK
_READ_ACCESS_TIME
ADI_EBIU_RESULT_INVALID_ASYNCH_BANK
_WRITE_ACCESS_TIME
ADI_EBIU_RESULT_INVALID_ASYNCH_BANK
_SETUP_TIME
ADI_EBIU_RESULT_INVALID_ASYNCH_BANK
_HOLD_TIME
4-14
Explanation
Command is not recognized.
Function completed successfully.
EBIU module is not initialized.
Invalid self-refresh value is specified. See
"ADI_EBIU_SDRAM_TCSR" on page
Invalid power-up start delay bit value is speci-
fied. See "ADI_EBIU_SDRAM_EBUFE" on
page 4-42.
Invalid SDRAM power-up sequence bit value is
specified. See
on page 4-42.
Invalid external buffering bit value is specified.
See "ADI_EBIU_SDRAM_SRFS" on page
Invalid fast back-to-back, read-to-write bit value
is specified. See
"ADI_EBIU_SDRAM_FBBRW" on page
Invalid control disable during bus grant bit value
is specified. See
"ADI_EBIU_SDRAM_CDDBG" on page
Invalid SDRAM enable selection. See
"ADI_EBIU_SDRAM_ENABLE" on page 4-38
Invalid asynchronous memory read access time
Invalid asynchronous memory write access time
Invalid asynchronous memory bank setup time
Invalid asynchronous memory bank hold time
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
"ADI_EBIU_SDRAM_PUPSD"
4-41.
4-41.
4-43.
4-44.