Dual-Core Considerations; Using Automatic Synchronization - Analog Devices VisualDSP++ 5.0 Service Manual

Optimal Power Consumption
The following statement requests the PM module set the core and system
clock frequencies to the maximum that can be sustained at a voltage level
of 0.85 V.
adi_pwr_SetMaxFreqForVolt(ADI_PWR_VLEV_085);

Dual-Core Considerations

The following sections explain how to use system services with a dual-core
configuration.

Using Automatic Synchronization

The PLL programming sequence for a dual-core processor requires that
both cores be brought to the IDLE state while changes are applied to the
and registers. A dual-core processor may execute a program on each
PLL VR
core, or it may execute a program on just one core. When both cores are
used to execute a program, a mechanism is required for both cores to go to
the IDLE state, and stay there while the registers are written. The power
management module provides a mechanism that uses the supplemental
interrupt to synchronize the cores for PLL programming. This mechanism
is invoked automatically by calling the
cores and passing the command
with a NULL argument, as shown in the following command-pair table
for the ADSP-BF561 EZ-KIT Lite.
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
Power Management Module
adi_pwr_Init()
ADI_PWR_CMD_SET_AUTO_SYNC_ENABLED
function on both
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