Analog Devices VisualDSP++ 5.0 Service Manual page 196

Setting Control Values in the EBIU Module
Table 4-3. ADI_EBIU_COMMAND Data Values (Cont'd)
Command
ADI_EBIU_CMD_SET_SDRAM_FBBRW
ADI_EBIU_CMD_SET_SDRAM_CDDBG
ADI_EBIU_CMD_SET_SDRAM_PUPSD
ADI_EBIU_CMD_SET_SDRAM_PSM
ADI_EBIU_CMD_SET_ASYNCH_BANK_
TRANSITION_TIME
ADI_EBIU_CMD_SET_ASYNCH_BANK_READ_
ACCESS_TIME
ADI_EBIU_CMD_SET_ASYNCH_BANK_WRITE_
ACCESS_TIME
4-32
Associated Data Value
ADI_EBIU_SDRAM_FBBRW
whether to enable/disable fast back-to-back
read/write operations. See
"ADI_EBIU_SDRAM_FBBRW" on page
ADI_EBIU_SDRAM_CDDBG
whether to enable/disable SDRAM control sig-
nals when the external memory interface is
granted to an external controller. See
"ADI_EBIU_SDRAM_CDDBG" on page
ADI_EBIU_SDRAM_PUPSD
whether the power-up start sequence is delayed
by 15 cycles. See
SCLK
"ADI_EBIU_SDRAM_PUPSD" on page
ADI_EBIU_SDRAM_PSM
of events in the power-up start sequence. See
"ADI_EBIU_SDRAM_PSM" on page
ADI_EBIU_ASYNCH_BANK_TIMING
ing an
ADI_EBIU_BANK_NUMBER
ADI_EBIU_TIMING_VALUE
transition time in either cycles or timing units.
See "ADI_EBIU_ASYNCH_BANK_TIMING"
on page 4-29.
ADI_EBIU_ASYNCH_BANK_TIMING
ing an
ADI_EBIU_BANK_NUMBER
ADI_EBIU_TIMING_VALUE
access time in either cycles or timing units. See
"ADI_EBIU_ASYNCH_BANK_TIMING" on
page 4-29.
ADI_EBIU_ASYNCH_BANK_TIMING
ing an
ADI_EBIU_BANK_NUMBER
ADI_EBIU_TIMING_VALUE
write access time in either cycles or timing units.
See "ADI_EBIU_ASYNCH_BANK_TIMING"
on page 4-29.
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
value specifying
4-43.
value specifying
4-44.
value specifying
4-42.
value specifying the order
4-43.
value specify-
and an
that specifies the
value specify-
and an
that specifies the read
value specify-
and an
that specifies the