Adi_Pwr_Setpowermode - Analog Devices VisualDSP++ 5.0 Service Manual

Power Management API Reference

adi_pwr_SetPowerMode

Description
This function sets the power mode of the processor. There are five modes:
• Full-On. The processor core clock (
run at the frequencies set via the
adi_pwr_SetVoltageRegulator
• Active. The PLL is bypassed so that the processor core clock and
system clock run at the
is available to configured L1 memories appropriately.
• Sleep. The core processor is idled. The system clock continues to
run at the speed set via the
adi_pwr_SetVoltageRegulator
external memory.
• Deep Sleep. The processor core and all peripherals, except the
real-time clock (RTC), are disabled. DMA is not supported in this
mode.
SDRAM is set to self-refresh mode. The voltage regulator is
powered up on RTC interrupt or a hardware reset event. In both
cases, the core reset sequence is initiated.
• Hibernate. The internal voltage regulator is powered down.
SDRAM is set to self-refresh mode. The voltage regulator is
powered up on hardware reset.
Until SDRAM is properly configured and the refresh rate is
appropriate, data held in SDRAM will decay. This only applies to
exiting hibernate or deep sleep mode by a hardware reset event. For
ADSP-BF531, ADSP-BF532, and ADSP-BF533 processor cores,
the
SCKE
SDRAM to exit self-refresh mode. This behavior is a constraint of
3-36
CLKIN
pin on the processor is asserted on reset, causing the
VisualDSP++ 5.0 Device Drivers and System
) and system clock (
CCLK
adi_pwr_SetFreq
functions. Full DMA is enabled.
input clock frequency. DMA access
or
adi_pwr_SetFreq
functions. DMA is restricted to
Services Manual for Blackfin Processors
)
SCLK
or