Analog Devices VisualDSP++ 5.0 Service Manual page 625

peripheral DMA
adi_dev_Read function,
adi_pdd_Read function,
described, 6-6
peripheral ID
defined, 8-7
identifying, 8-29
peripheral interrupts, 2-2
peripheral timer, 8-7
physical device driver
API, 10-83
API description, 10-47
custom-defined error codes,
defined, 10-5
design overview, 10-45
entry point, 10-34, 10-50
extensions, 10-48
handles, 10-51
shutdown procedure,
source code, 10-50
PLL controller
resetting, 3-30
reset to hardware reset values,
PLL control register
DF bit, 3-48
input delay bit, 3-48
output delay bit, 3-48
PLL_DIV register
adi_pwr_AdjustFreq function,
adi_pwr_SetFreq function,
setting core clock divider bit field,
setting system clock divider bit field,
3-52
PLL input divider, 3-33
PLL_LOCKCNT register,
PLL_STAT register, 3-43
port control manager
assigning programmable flag pins to
functions, 9-2
defined, 9-2
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
10-37
10-54
10-49
1-24
3-31
3-16
3-33
3-47
3-43
port control manager
enumeration types, 9-17
initializing, 9-6
return codes, 9-16
terminating, 9-7
port control registers, 7-2
POSIX functions, 12-65
power management module
API functions, 3-15
defined, 3-1
enabling, 4-2
enumerations, 3-42
initialization values,
initializing, 3-24
macros, 3-56
public data types, 3-42
return codes, 3-50
power modes
active, 3-36
current, 3-22
deep sleep, 3-36
full-on, 3-36
hibernate, 3-36
processor, 3-36
sleep, 3-36
specifying, 3-49
power saving value, for current PLL and
voltage regulator settings,
PPI channel, enabling,
PPIEntryPoint variable,
precharge all command,
precharge command, 4-16
PrepareBufferList function, 10-37,
PrepareBufferList function, configuring
DMA configuration control register,
10-43
processor power mode, setting, 3-36,
processor variants, 1-12,
programmable flags, 7-1
Index
(continued)
3-24
3-23
9-8
10-50
4-43
10-43
3-49
1-26
I -17