Analog Devices VisualDSP++ 5.0 Service Manual page 620

Index
DevNumber parameter,
DMA
commands, 6-62
memory transfer, 6-46
one-dimensional memory copy,
one-dimensional transfers,
two-dimensional memory copy,
two-dimensional transfers, 6-9,
DMACallback function, 10-41,
DMA channel ID, detecting,
DMA channels
closing, 6-21, 6-36
configuration, 6-20
controlling, 6-3, 6-37
identifying, 6-39
ID values, 6-58
opening, 6-11, 6-48
specifying, 6-50
DMA configuration control register, 6-12,
6-55, 10-43
DMA configuration control word,
DMA controller
circular transfer operating mode,
DMA manager, 6-3
identifying, 6-39
interface to, 6-2
large descriptor chain mode,
operating modes, 6-12
single transfer operating mode,
small descriptor mode,
DMA manager
API, 6-32
defined, 6-2
initializing, 6-4, 6-40
loopback submode, 6-24
return codes, 6-60
streaming submode,
terminating, 6-5, 6-52
DMA peripheral map (PMAP) ID,
DMA traffic control, 6-31
I -12
10-10
6-42
6-8
6-44
6-29
10-42
6-27
6-56
6-15
6-16
6-12
6-20
6-25
10-53
VisualDSP++ 5.0 Device Drivers and System
DMAx_CONFIG register, field values,
6-61
dynamic memory usage,
dynamic power management, power
management (PM) module,
dynamic power management registers,
configuring,
E
EBIU module
API functions,
controlling the configuration of,
defined, 4-1
enumerations,
initialization values,
initializing, 4-16
public data types,
return codes,
setting control values,
EBIU_SDBCTL register
EBCAW bits,
EBSZ bits, 4-39
setting, 4-16
EBIU_SDGCTL register,
CDDBG bit,
EBUFE bit, 4-42
EMREN bit,
FBBRW bit, 4-43
PASR bits, 4-41
PSM bit, 4-43
PUPSD bit, 4-42
SCTLE bit, 4-40
setting, 4-16
SRFS bit, 4-41
TCSR bits, 4-41
EBIU SDRAM registers, configuring,
EBIU_SDRRC register
adi_ebiu_AdjustSDRAM function,
adjusting SDRAM refresh rate,
setting, 4-16
Services Manual for Blackfin Processors
12-13
3-2
3-18
4-10
4-31
4-24
4-16
4-24
4-24
4-31
4-39
4-11
4-44
4-40
4-12
4-11
4-18