Adi_Ebiu_Init - Analog Devices VisualDSP++ 5.0 Service Manual

EBIU API Reference

adi_ebiu_Init

Description
The
adi_ebiu_Init
module is configured to handle either a DDR or a SDRAM controller,
plus an asynchronous memory controller. For the EBIU service which
supports SRDRAM, the
, and
EBIU_SDBCTL
figuration attached to the processor. For the EBIU service that supports
DDR, the
adi_ebiu_Init
,
DDRCTL0 DDRCTL1
SDRAM or the DDR controller, certain values must be passed to
adi_ebiu_Init
and one for DDR. The following table shows the values that must be
passed to
adi_ebiu_Init
Description
Bank size
Bank column
address width
1
CAS latency
threshold (MHz)
2
Minimum TRAS
(ns)
3
Min. TRP (ns)
4
Min. TRCD (ns)
5
Min. TWR
(cycles, ns)
Refresh period
(cycles, ms)
1 Column address strobe
2 Required delay between issuing a
and between the
4-16
function initializes the EBIU module. Currently, the
adi_ebiu_Init
registers to reflect the correct SDRAM con-
EBIU_SDRRC
function sets up the DDR control registers,
, and . For successful initialization of the
DDRCTL2
, as outlined in the following two tables, one for SDRAM
to initialize SDRAM.
Command
ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE
ADI_EBIU_CMD_SET_SDRAM_BANK_COLUMN_WIDTH
ADI_EBIU_CMD_SET_SDRAM_CL_THRESHOLD
ADI_EBIU_CMD_SET_SDRAM_TRASMIN
ADI_EBIU_EBIU_CMD_SET_SDRAM_TRPMIN
ADI_EBIU_CMD_SET_SDRAM_TRCDMIN
ADI_EBIU_CMD_SET_SDRAM_TWRMIN
ADI_EBIU_CMD_SET_SDRAM_REFRESH
Bank Activate
command and the exit from self-refresh.
Self-Refresh
VisualDSP++ 5.0 Device Drivers and System
function sets up the
command and a
Services Manual for Blackfin Processors
EBIU_SDGCTL
Value Type
ADI_EBIU_SDRAM_BANK_VALUE
ADI_EBIU_SDRAM_BANK_VALUE
u32
ADI_EBIU_TIME
ADI_EBIU_TIME
ADI_EBIU_TIME
ADI_EBIU_TIMING_VALUE
ADI_EBIU_TIMING_VALUE
command,
Precharge
,