Analog Devices VisualDSP++ 5.0 Service Manual page 200

Setting Control Values in the EBIU Module
Table 4-3. ADI_EBIU_COMMAND Data Values (Cont'd)
Command
ADI_EBIU_CMD_SET_DDR_WR
ADI_EBIU_CMD_SET_DDR_PASR
ADI_EBIU_CMD_SET_DDR_SOFT_RESET
ADI_EBIU_CMD_MOBILE_DDR_ENABLE
ADI_EBIU_CMD_SET_FREQ_AS_MHZ
ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_
ENABLE
ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_
POLARITY
ADI_EBIU_CMD_SET_ASYNCH_BANK_16_BIT_
PACKING_ENABLE
ADI_EBIU_CMD_SET_ASYNCH_BANK_ENABLE
4-36
Associated Data Value
Set DDR write recovery time
Set DDR partial array self-refresh (mobile only)
0=full array, 1=half, 2=quarter,
5=eighth, 6=sixteenth
Issue DDR soft reset
Enable mobile DDR
Sets DDR frequency units to megahertz
ADI_EBIU_ASYNCH_BANK_VALUE
bank number and an
ADI_EBIU_ASYNCH_BANK_ARDY_ENABLE
specifies whether the
for this bank. See
"ADI_EBIU_ASYNCH_BANK_ARDY_ENAB
LE" on page
ADI_EBIU_ASYNCH_BANK_VALUE
bank number and an
ADI_EBIU_ASYNCH_BANK_ARDY_POLARITY
specifies the polarity of the
that indicates the completion of the access time.
See
"ADI_EBIU_ASYNCH_BANK_ARDY_POLA
RITY" on page
For ADSP-BF561 processors only
ADI_EBIU_ASYNCH_BANK_VALUE
bank number and an
ADI_EBIU_ASYNCH_BANK_DATA_PATH
fies whether or not 16-bit packing is enabled. See
"ADI_EBIU_ASYNCH_BANK_DATA_PATH"
on page 4-45.
ADI_EBIU_ASYNCH_BANK_ENABLE
ing which banks to enable. See
"ADI_EBIU_ASYNCH_BANK_ENABLE" on
page 4-45.
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
specifying a
input will be sampled
ARDY
4-46.
specifying a
input sample
ARDY
4-46.
specifying a
value specify-
that
that
that speci-