Adi_Pwr_Adjustfreq - Analog Devices VisualDSP++ 5.0 Service Manual

Power Management API Reference

adi_pwr_AdjustFreq

Description
This function allows the core and system clocks to be modified by specify-
ing the core and system clock divider ratios,
register. The processor is not idled.
Prototype
ADI_PWR_RESULT adi_pwr_AdjustFreq(
const ADI_PWR_CSEL csel,
const ADI_PWR_SSEL ssel
);
Arguments
csel ADI_PWR_CSEL
divided to obtain a new core clock frequency. The divider value cannot exceed the
value.
ssel
See "ADI_PWR_CSEL" on page
ssel ADI_PWR_SSEL
system clock frequency.
See "ADI_PWR_SSEL" on page
Return Value
In the debug variant of the library, the function
returns one of the following result codes; otherwise, the function returns
ADI_PWR_RESULT_SUCCESS
ADI_PWR_RESULT_SUCCESS
ADI_PWR_RESULT_NOT_INITIALIZED
ADI_PWR_RESULT_INVALID_CSEL
3-16
value specifies how the voltage core oscillator (VCO) frequency is
3-47.
value specifies how the VCO frequency is divided to obtain a new
3-52.
.
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
and , in the
CSEL SSEL
adi_pwr_AdjustFreq
Process completed successfully.
PM module has not been initialized.
Invalid value for has been specified.
CSEL
PLL_DIV