Adi_Pwr_Vr_Clkbufoe; Adi_Pwr_Vr_Freq; Adi_Pwr_Vr_Gain - Analog Devices VisualDSP++ 5.0 Service Manual

ADI_PWR_VR_CLKBUFOE

This data type defines the valid values for the
regulator control register. If enabled, the
peripheral devices, especially the Ethernet PHY.
ADI_PWR_VR_CLKBUFOE_DISABLED
ADI_PWR_VR_CLKBUFOE_ENABLED

ADI_PWR_VR_FREQ

This data type defines the acceptable switching frequency values for the
voltage regulator. Its value is linked to the switching capacitor and induc-
tor values. The higher the frequency setting, the smaller the capacitor and
inductor values. The valid values for all Blackfin processors are:
ADI_PWR_VR_FREQ_POWERDOWN
ADI_PWR_VR_FREQ_333KHZ
ADI_PWR_VR_FREQ_667KHZ
ADI_PWR_VR_FREQ_1MHZ

ADI_PWR_VR_GAIN

This data type defines the acceptable values for the internal loop gain of
the switching regulator loop. The gain controls how quickly the voltage
output settles on its final value. The higher the gain, the quicker the set-
tling time. High gain settings cause greater overshoot in the process.
ADI_PWR_VR_GAIN_5
ADI_PWR_VR_GAIN_110
ADI_PWR_VR_GAIN_20
ADI_PWR_VR_GAIN_50
VisualDSP++ 5.0 Device Drivers and System
Services Manual for Blackfin Processors
Power Management Module
CLKBUFOE
signal can be shared with
CLKIN
Disable
CLKIN
Enable sharing.
CLKIN
Power-down/bypass onboard regulation
333 kHz
667 kHz
1 MHz (default)
5
10
20 (default)
50
bit in the voltage
sharing.
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