Lcdc Control Register (Lcdcc) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 24 LCD CONTROLLER
24.4.1

LCDC Control Register (LCDCC)

The LCDC control register (LCDCC) is used to set the clock, display mode, and power
supply control.
LCDC Control Register (LCDCC)
Address
0FC4
H
FCH :
FCL :
R/W :
446
Figure 24.4-2 LCDC Control Register (LCDCC)
bit7 bit6 bit5 bit4
CSS VSEL
LCDEN
R/W R/W R/W R/W
FP1
MS1
VSEL
LCDEN
CSS
Main oscillation frequency
Sub oscillation frequency
Readable/writable (Read value is the same as write value)
: Initial value
bit3 bit2 bit1
BK MS1 MS0 FP1
R/W R/W R/W
FP0
Main clock (CSS = 0)
0 0
16
2 x N/FCH
0 1
17
2 x N/FCH
1 0
18
2 x N/FCH
1 1
19
2 x N/FCH
MS0
0 0
0 1
1/2 duty output mode (time division number N = 2)
1 0
1/3 duty output mode (time division number N = 3)
1 1
1/4 duty output mode (time division number N = 4)
BK
Display blanking select bit
0
1
Display blanking
LCD drive power supply control bit
With internal divider resistors selected
0
Use external divider resistors.
1
Use internal divider resistors.
Main stop/watch mode operation enable bit
0
Disable operation.
1
Enable operation.
Frame period generation clock select bit
0
1
bit0 Initial value
FP0 00010000
R/W
Frame period select bits
Subclock (CSS = 1)
7
2 x N/FCL
8
2 x N/FCL
9
2 x N/FCL
10
2 x N/FCL
Display mode select bits
LCD operation halt
Display
Main clock
Subclock
B