Fujitsu F2MC-8FX Hardware Manual page 203

Interval time
The interval time varies depending on the timing for clearing the hardware watchdog timer. Figure 12.4-1
shows the correlation between the clearing timing of the hardware watchdog timer and the interval time.
Figure 12.4-1 Clearing Timing and Interval Time of hardware watchdog Timer
Minimum time
RC oscillator
prescalar output
Watchdog 1-bit
counter
Watchdog reset
Maximum time
RC oscillator
prescalar output
Watchdog 1-bit
counter
Watchdog reset
Operation in the subclock mode
When a hardware watchdog reset is generated in the subclock mode, the timer starts operating in the main
clock mode after the oscillation stabilization wait time has elapsed. The reset signal is outputted during this
oscillation stabilization wait time.
Setup Procedure Example
The hardware watchdog timer is set up in the following procedure:
• Clear the hardware watchdog timer.(HWDC:WTE3 to WTE0 = 0101
327ms (MAX)/655ms(TYP)
Watchdog cle ar
2.62s(MIN)/1.31s(TYP)
Watchdog cle ar
CHAPTER 12 HARDWARE WATCHDOG TIMER
Overflo
Overflow
)
B
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