Hardware Watchdog Timer Control Register (Hwdc) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 12 HARDWARE WATCHDOG TIMER
12.3.1

Hardware Watchdog Timer Control Register (HWDC)

The hardware watchdog timer control register (HWDC) activates or clears the hardware
watchdog timer.
Hardware Watchdog Timer Control Register (HWDC)
Figure 12.3-2 Hardware Watchdog Timer Control Register (HWDC)
Address
bit7
000D
-
H
R0/WX
R/W : Readable/writable (Read value is the same as write value)
R0/WX : Undefined bit (Read value is "0", writing has no effect on operation)
R0/W0 : Reserved bit (Read value is "0", always write "0")
- : Not used
: Initial value
F : Main clock
CH
F : Sub clock
CL
186
bit6 bit5 bit4
Reserved
-
Reserved
R0/WX R0/WX
R0/WX
WTE3 WTE2 WTE1 WTE0
1 0
0
Other than above
bit3 bit2 bit1
WTE3 WTE2 WTE1
R0,W R0,W R0,W
Watchdog control bits
Clear watchdog timer
1
No effect on operation
Initial value
bit0
00000000
WTE0
B
R0,W