Fujitsu F2MC-8FX Hardware Manual page 79

CHAPTER 6 CLOCK CONTROLLER
Figure 6.7-2 Clock Mode State Transition Diagram (Single System Clock Product)
Power on
Reset occurs in each state.
Reset state
<1>
<2>
Main clock oscillation
stabilization wait time
(5)
Main PLL
Main clock mode
clock mode
(4)
Main PLL clock
(3)
oscillation stabiliza-
tion wait time
65