Operations Of Clock Supervisor - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 26 CLOCK SUPERVISOR
26.4

Operations of Clock Supervisor

This section describes the operations of the clock supervisor.
Operations of Clock Supervisor
The clock supervisor monitors the main clock and sub clock oscillations. If main clock and sub clock
oscillations have halted, the device switches to an CR clock and generates a reset.
The following describes the operation in each clock mode.
Main clock oscillation halt in main clock mode
The clock supervisor detect that main clock oscillation has halted, if no rising edge is detected on the main
clock for 4 CR clock cycles in main clock mode.
If a main clock halt is detected, a reset is generated and the main clock switches to the CR clock.
The clock supervisor may detect incorrectly, if main clock is a low speed (longer than 4 CR clock cycles).
It results from using the CR clock for detecting that main clock oscillation have halted.
The clock supervisor does not detect the main clock during stop mode.
Sub clock oscillation halt in main clock mode (only on dual clock products)
In main clock mode, the condition used to detect the sub clock oscillation as having halted is that no rising
edge is detected on the sub clock for 32 CR clock cycles.
Although no reset is generated immediately if a sub clock halt is detected in main clock mode, the sub
clock switches to CR clock divided by two.
A reset can be generated when the device switches from main clock mode to sub clock mode with a sub clock
oscillation halt detected, by setting the SRST bit in the clock supervisor control register (CSVCR).
Because the CR clock is used to detect whether the sub clock has halted, a sub clock halt may be detected if
the sub clock is set to a low speed (period longer than 32 CR clock cycles).
The clock supervisor does not detect the sub clock during stop mode.
Sub clock oscillation halt in sub clock mode (only on dual clock products)
In sub clock mode, the condition used to detect the sub clock oscillation as having halted is that no rising
edge is detected on the sub clock for 34 CR clock cycles.
If a sub clock halt is detected, a reset is generated and the device enters main clock mode. In this case, the
sub clock switches to CR clock divided by two.
As the CR clock is used to detect whether the sub clock has halted, a sub clock halt may be detected if the
sub clock is set to a low speed (period longer than 32 CR clock cycles).
The clock supervisor does not detect the sub clock during the stop mode.
Main clock oscillation halt in sub clock mode (only on dual clock products)
In sub clock mode, the main clock oscillation remains halted and is therefore not detected by the clock
supervisor.
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