Fujitsu F2MC-8FX Hardware Manual page 411

Start Conditions
While the bus is idle (SCL0 and SDA0 are both at the logical "H" level), the master generates a start
condition to start transmission. As shown in Figure 22.7-1, a start condition is triggered when the SDA0
line is changed from "H" to "L" while SCL0 = "H". This starts a new data transfer and commences master/
slave operation.
A start condition can be generated in either of the following two ways.
• By writing "1" to the IBCR10:MSS bit while the I
0, IBCR10:INT = 0, and IBCR00:ALF = 0). (Next, IBSR0:BB is set to "1" to indicate that the bus is
busy.)
• By writing "1" to the IBCR10:SCC bit during an interrupt while in bus master mode (IBCR10:MSS = 1,
IBSR0:BB = 1, IBCR10:INT = 1, and IBCR00:ALF = 0). (This generates a repeated start condition.)
Writing "1" to the IBCR10:MSS or IBCR10:SCC bit is ignored in other than the above cases. If another
system is using the bus when "1" is written to the IBCR10:MSS bit, the IBCR00:ALF bit is set to "1".
Addressing
Slave addressing in master mode
In master mode, IBSR0:BB and IBSR0:TRX are set to "1" after the start condition is generated, and the
slave address in the IDDR0 register is output to the bus starting with the MSB. The address data consists of
eight bits: the 7-bit slave address and the data transfer direction R/W bit (bit 0 of IDDR0).
The acknowledgment from the slave is received after the address data is sent. SDA0 goes to "L" in the
ninth clock cycle and the acknowledge bit from the receiving device is received (see Figure 22.7-1). In this
case, the R/W bit (IDDR0:bit0) is inverted logically and stored in the IBSR0:TRX bit as "1" if the SDA
level is "L".
Addressing in slave mode
In slave mode, after the start condition is detected, IBSR0:BB is set to "1" and IBSR0:TRX is set to "0",
and the data received from the master is stored in the IDDR0 register. After the address data is received, the
IDDR0 and IAAR0 registers are compared. If the addresses match, IBSR0:AAS is set to "1" and an
acknowledgment is sent to the master. Next, bit 0 of the receive data (bit 0 of the IDDR0 register) is saved
in the IBSR0:TRX bit.
Data Transfer
If the MCU is addressed as a slave, data can be sent or received byte by byte with the direction determined
by the R/W bit sent by the master.
Each byte to be output on the SDA0 line is fixed at eight bits. As shown in Figure 22.7-1, the receiver
sends an acknowledgment to the sender by forcing the SDA0 line to the stable "L" level while the
acknowledge clock pulse is "H". Data is transferred at one clock pulse per bit with MSB at the head.
Sending and receiving an acknowledgment is required after each byte is transferred. Accordingly, nine
clock pulses are required to transfer one complete data byte.
2
C bus is not in use (IBCR10:MSS = 0, IBSR0:BB =
2
CHAPTER 22 I C
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