Interrupts Of Timebase Timer - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 10 TIMEBASE TIMER
10.4

Interrupts of Timebase Timer

An interrupt request is triggered when the interval time selected by the timebase timer
elapses (interval timer function).
Interrupt when Interval Function is in Operation
When the timebase timer counter counts down using the internal count clock and the selected timebase
timer counter underflows, the timebase timer interrupt request flag bit (TBTC:TBIF) is set to "1". If the
timebase timer interrupt request enable bit is enabled (TBTC:TBIE = 1), an interrupt request (IRQE) will
be generated to interrupt controller.
• Regardless of the value of TBIE bit, TBIF bit is set to "1", when the selected bit underflows.
• When TBIF bit is set to "1" and TBIE bit is changed from the disable state to the enable state (0 → 1),
an interrupt request is generated immediately.
• TBIF bit is not set when the counter is cleared (TBTC:TCLR = 1) and the timebase timer counter
underflows at the same time.
• Write "1" to TBIF bit to clear an interrupt request in an interrupt processing routine.
Note:
When enabling the output of interrupt requests after canceling a reset (TBTC:TBIE = 1), always clear
TBIF bit at the same time (TBTC:TBIF = 0).
Table 10.4-1 Interrupts of Timebase Timer
Interval condition
Interrupt flag
Interrupt enable
164
Item
Interval time set by "TBTC:TBC1" and "TBC0" has elapsed
TBTC:TBIF
TBTC:TBIE
Description