Fujitsu F2MC-8FX Hardware Manual page 368

CHAPTER 20 UART/SIO
• Write transmit data to the UART/SIO serial output data register, then set the transmission operation
enable bit (TXE) to "1" to generate the serial clock signal and start reception.
When 5 to 8-bit serial data is received by the reception shift register, the received data is transferred to the
UART/SIO serial input data register (RDR0) and the next piece of serial data can be received.
When the serial input data register stores data, the receive data register full (RDRF) bit is set to "1".
A reception interrupt occurs the moment the receive data register full (RDRF) bit is set to "1" when the
reception interrupt enable bit (RIE) contains "1".
To read received data, read it from the UART/SIO serial input data register after checking the error flag
(OVE) in the UART/SIO serial status and data register.
When received data is read from the UART/SIO serial input data register (RDR0), the receive data register
full (RDRF) bit is cleared to "0".
UCK
UI
Read to RDR0
RDRF
Operation when reception error occurs
When an overrun error (OVE) exists, received data is not transferred to the UART/SIO serial input data
register (RDR0).
Overrun error (OVE)
Upon completion of reception for serial data, the overrun error (OVE) bit is set to "1" if the receive data
register full (RDRF) bit has been set to "1" by the reception for the preceding piece of data.
UCK
UI
Read to
RDR0
RDRF
OVE
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Figure 20.7-12 8-bit Reception of Synchronous CLK Mode
D0 D1 D2 D3 D4 D5 D6 D7
...
D0 D1 ... D6 D7
Interrupt to interrupt controller
...
D0 D1 ... D6 D7
...
D0 D1 ... D6 D7