Fujitsu F2MC-8FX Hardware Manual page 308

CHAPTER 17 16-BIT PPG TIMER
Invalidating the retrigger (RTRG of PCNTH0 register: bit 4 = 0)
16-bit down counter value
m
n
0
Software trigger
PPG
(Normal polarity)
(Inverted polarity)
Validating the retrigger (RTRG of PCNTH0 register: bit 4 = 1)
Counter value
m
n
0
Software trigger
PPG
(Normal polarity)
PPG
(Inverted polarity)
294
Figure 17.7-1 When Retrigger Is Invalid in PWM Mode
Rising edge detected
(1)
(2)
(1)=n × T ns
(2)=m × T ns
Figure 17.7-2 When Retrigger Is Valid in PWM Mode
Rising edge detected
(1)=n × T ns
(2)=m × T ns
Trigger ignored
T : Count clock cycle
m: PCSRH0 & PCSRL0 register value
n : PDUTH0 & PDUTL0 register value
Restarted by trigger
(1)
(2)
T : Count clock cycle
m: PCSRH0 & PCSRL0 register value
n : PDUTH0 & PDUTL0 register value
Time
Time