Fujitsu F2MC-8FX Hardware Manual page 461

Table 24.4-1 Functions of Bits in LCDC Control Register (LCDCC)
Bit name
CSS:
Frame period
bit7
generation clock select
bit
LCDEN:
bit6 Main stop/watch mode
operation enable bit
VSEL:
bit5 LCD driving power
control bit
BK:
bit4 Display blanking select
bit
MS1,
bit3 MS0:
bit2 Display mode select
bits
FP1,
bit1 FP0:
bit0 Frame period select
bits
Selects the clock to generate the frame period for LCD display.(in product of single system clock,
always write "0" to this bit)
• When this bit is "0", the LCD controller operates with the output of the timebase timer driven by
the main clock oscillation. When the bit is "1", the LCD controller operates with the output of the
watch prescaler driven by the subclock.
Note: As the main clock stops oscillation in main stop mode and subclock mode, the LCD
controller cannot operate with the output of the timebase timer in these modes.
Shifting the main clock speed (using the gear function) during operation with the timebase timer
output does not affect the frame period.
LCD display may flicker when the clock speed is being shifted. Before shifting it, therefore,
temporarily halt the display, for example, by using blanking (LCDCC:BK = 1).
Specifies whether the LCD controller is to continue to operate in main stop and watch (timebase
timer) modes.
When the bit is "0", LCD display stops.
When this bit is "1", LCD display continues even after transition to main stop or watch mode.
Note: The subclock must be selected (CSS = 1) to continue operating in main stop or watch
mode.
In models with internal divider resistors, this bit selects whether to energize the internal divider
resistors.
Setting the bit to "0": Shuts off the internal divider resistors.
Setting the bit to "1": Energizes the internal divider resistors. To connect external divider
resistors, set this bit to "0".
Selects whether to display or blank the LCD.
• When display blanking (no display, BK = 1) is selected, the segment output changes to a
deselected waveform (waveform not treated as a display condition).
Select one of three output waveform duties.
• The common pin to be used is determined depending on the selected duty output mode.
• When these bits are "00 ", the LCD controller driver stops the display operation.
B
Note: If the selected frame period generation clock can halt, for example, upon transition to stop
mode, halt the display operation (MB1, MS0 = 00) in advance.
As LCD display may flicker upon switching, halt the display temporarily, for example, by using
blanking (LCDCC:BK = 1) before switching.
Select one of four LCD display frame periods.
Note: Set the registers after calculating the optimum frame frequency according to the LCD
module to be used. The frame period is affected by the source oscillation frequency.
As LCD display may flicker upon switching, halt the display temporarily, for example, by using
blanking (LCDCC:BK = 1) before switching.
CHAPTER 24 LCD CONTROLLER
Function
447