Fujitsu F2MC-8FX Hardware Manual page 193

Interval time
The interval time varies depending on the timing for clearing the watchdog timer. Figure 11.4-1 shows the
correlation between the clearing timing of the watchdog timer and the interval time when the timebase
timer output 2
Figure 11.4-1 Clearing Timing and Interval Time of Watchdog Timer
Minimum time
Timebase timer
count clock output
Watchdog 1-bit
counter
Watchdog reset
Maximum time
Timebase timer
count clock output
Watchdog 1-bit
counter
Watchdog reset
Operation in the subclock mode
When a watchdog reset is generated in the subclock mode, the timer starts operating in the main clock
mode after the oscillation stabilization wait time has elapsed. The reset signal is outputted during this
oscillation stabilization wait time.
Setup Procedure Example
The watchdog timer is set up in the following procedure:
1) Select the count clock.
2) Activate the watchdog timer.
3) Clear the watchdog timer.
21
F (F : main clock) is selected as the count clock (main clock = 4MHz).
CH CH
Watchdog clear
Watchdog clear
524ms
Overflow
1.05s
(WDTC:CS1, CS0)
(WDTC:WTE3 to WTE0 = 0101
(WDTC:WTE3 to WTE0 = 0101
CHAPTER 11 WATCHDOG TIMER
Overflow
)
B
)
B
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