Fujitsu F2MC-8FX Hardware Manual page 59

Block Diagram of the Clock Controller
Figure 6.1-1 shows the block diagram of the clock controller.
PLL controller register (PLLC)
MPEN MPMC1 MPMC0MPRDY
F
(2)
CL
Subclock
oscillator
circuit
Subclock control
(1)
Main clock
F
CH
oscillator circuit
Main clock control
SCM1 SCM0 SCS1 SCS0 SRDY SUBS DIV1 DIV0
System clock control register (SYCC)
(1): Main clock (F )
CH
(2): Subclock (F )
CL
(3): Main clock
(4): Subclock
Figure 6.1-1 Clock Controller Block Diagram
- - -
-
System clock selector
(4)
Divide by 2
(6)
(3)
Divide by 2
(5)
Main PLL
oscillator
Source clock
circuit
control circuit
Oscillation
stabilization
wait circuit
(5): Main PLL clock
(6): Source clock
(7): Machine clock (MCLK)
CHAPTER 6 CLOCK CONTROLLER
Standby control register (STBC)
STP SLP SPL SRST TMD
Prescaler
No division
Divide by 4
Clock
(7)
Divide by 8
control
Divide by 16
circuit
selection
SWT3 SWT2 SWT1 SWT0 MWT3 MWT2 MWT1 MWT0
Oscillation stabilization wait time setting register (WATR)
- - -
Stop signal
Sleep signal
Clock for watch
prescaler
Watch or timebase
timer
Supply to CPU
Supply to peripheral
resources
Clock for timebase
timer
From timebase timer
14 1
2 /F to 2 /F
CH CH
From watch prescaler
15 1
2 /F to 2 /F
CL CL
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