Fujitsu F2MC-8FX Hardware Manual page 415

• Conditions (2) in which no interrupt is generated due to arbitration lost
If the program enables I
setting the IBCR10:MSS bit to "1") when the I
This is because, as shown in Figure 22.7-4, this I
bit= 0) if another master starts communications on the I
been disabled (ICCR0:EN bit = 0).
Figure 22.7-4 Timing Diagram with No Interrupt Generated with IBCR0:ALF = 1
Start condition
SCL0 pin
SDA0 pin
ICCR0:EN bit
IBCR10:MSS bit
IBCR00:ALF bit
IBSR0:BB bit
IBCR10:INT bit
If this situation can occur, use the following procedure to set up the module from the software.
1) Trigger a start condition from the program (by setting the IBCR10:MSS bit to "1").
2) Check the IBCR00:ALF and IBSR0:BB bits in the arbitration lost interrupt.
If IBCR00:ALF = 1 and IBSR0:BB = 0, clear the IBCR00:ALF bit to "0".
If IBCR00:ALF = 1 and IBSR0:BB = 1, clear the IBCR00:ALE bit to "0" and perform control as normal.
(Normal control means writing "0" to the IBCR00:INT bit in the INT interrupt to clear IBCR00:ALF.)
In other cases, perform control as normal (Normal control means writing "0" to the IBCR00:INT bit in
the INT interrupt to clear IBCR00:ALF.)
2
C operation (by setting the ICCR0:EN bit to "1") and triggers a start condition (by
2
C bus is in use by another master.
IBCR10:INT bit interrupt
does not occur in 9th clock cycle.
Slave address ACK
2
C module cannot detect the start condition (IBSR0:BB
2
C bus when the operation of this I
Data
CHAPTER 22 I
2
C module has
Stop
condition
ACK
0
0
401
2
C