Pll Control Register (Pllc) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 6 CLOCK CONTROLLER
6.4

PLL Control Register (PLLC)

The PLL control register (PLLC) controls the main PLL clock.
Configuration of PLL Control Register (PLLC)
Address
0006
H
R/W : Readable/writable (Read value is the same as write value)
R0/W0 : Undefined bit (Read value is "0", write data should be "0")
- : Unused
: Initial value
54
Figure 6.4-1 Configuration of PLL Control Register (PLLC)
bit7 bit6 bit5
MPEN MPMC1 MPMC0
R/W R/W R/W
MPRDY
MPMC1
bit3 bit2
bit4
MPRDY - -
R/W R0/W0 R0/W0
Main PLL clock oscillation stability bit
Indicates the main PLL clock oscillation stabilization
0
wait state or main PLL clock oscillation being stopped
1 Indicates main PLL clock oscillation being stable
Main PLL clock multiplier setting bits
MPMC0
0 0 Main clock x 1
0 1 Main clock x 2
1 0 Main clock x 2.5
1 1 Setting prohibited
MPEN Main PLL clock oscillation enable bit
0 Disables main PLL clock oscillation
1 Enables main PLL clock oscillation
Initial value
bit1
bit0
00000000
- -
R0/W0
R0/W0
B