Standby Control Register (Stbc) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 6 CLOCK CONTROLLER
6.6

Standby Control Register (STBC)

The standby control register (STBC) is used to control transition from the RUN state to
sleep mode, stop mode, timebase timer mode, or watch mode, set the pin state in stop
mode, timebase timer mode, and watch mode, and to control the generation of software
resets.
Standby Control Register (STBC)
Address
0008
H
R0,W : Write only (Writable, "0" is read)
R/W : Readable/writable (Read value is the same as write value)
R0/WX : Undefined bit (Read value is "0", writting has no effect on operation)
- : Unused
: Initial value
60
Figure 6.6-1 Standby Control Register (STBC)
bit7 bit5
bit6
SLP
STP SPL
R0,W R0,W
R/W
TMD
Read
Always reads
0
"0".
1 -
SRST
Read
0 Always reads "0".
1 -
SPL
Holds external pins in their immediately preceding state in stop mode, timebase
0
timer mode, or watch mode
Places external pins in a high impedance state in stop mode, timebase timer
1
mode, or watch mode.
SLP
Read
0 Always reads "0".
1 -
STP
Read
0 Always reads "0".
1 -
bit2
bit3
bit4
-
SRST TMD
R0/WX
R0,W R0,W
Watch bit
Has no effect on the operation.
Main clock mode
Main PLL clock mode
Causes transition to
timebase timer mode
Software reset bit
Has no effect on the operation
Generates a 3 machine clock reset signal
Pin state setting bit
Sleep bit
Has no effect on the operation
Causes transition to sleep mode
Stop bit
Has no effect on the operation
Causes transition to stop mode
Initial value
bit1 bit0
- -
00000000
R0/WX R0/WX
Write
Subclock mode
Causes transition to
watch mode
Write
Write
Write
B