Fujitsu F2MC-8FX Hardware Manual page 414

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CHAPTER 22 I C
Stop Condition
The master can release the bus and end communications by generating a stop condition. Changing the
SDA0 line from "L" to "H" while SCL0 is "H" generates a stop condition. This signals to the other devices
on the bus that the master has finished communications (referred to below as "bus free"). However, the
master can continue to generate start conditions without generating a stop condition. This is called a
repeated start condition.
Writing "0" to the IBCR10:MSS bit during an interrupt while in bus master mode (IBCR10:MSS = 1,
IBSR0:BB = 1, IBCR10:INT = 1, and IBCR00:ALF = 0) generates a stop condition and changes to slave
mode. In other cases, writing "0" to the IBCR10:MSS bit is ignored.
Arbitration
The interface circuit is a true multi-master bus able to connect multiple master devices. Arbitration occurs
when another master within the system simultaneously transfers data during a master transfer.
Arbitration occurs on the SDA0 line while the SCL0 line is at the "H" level. When the send data is "1" and
the data on the SDA0 line is "L" at the master, this is treated as arbitration lost. In this case, data output is
halted and IBCR00:ALF is set to "1". If this occurs, an interrupt is generated if arbitration lost interrupts
have been enabled (IBCR00:ALE = 1). If IBCR00:ALF is set to "1", the module sets IBCR10:MSS = 0 and
IBSR0:TRX = 0, clears TRX, and goes to slave receive mode.
If IBCR00:ALF is set to "1" when IBSR0:BB = 0, IBCR00:ALF is cleared only by writing "0". If
IBCR00:ALF is set to "1" when IBSR0:BB = 1, IBCR00:ALF is cleared only by clearing IBCR10:INT to
"0".
Conditions for generating an arbitration lost interrupt when IBSR0:BB = "0"
When a start condition is generated by the program (by setting the IBCR10:MSS bit to "1") at the timing
shown in Figure 22.7-3 or Figure 22.7-4, interrupt generation (IBCR10:INT bit = 1) is prohibited by
arbitration lost detection (IBCR00:ALF = 1).
• Conditions (1) in which no interrupt is generated due to arbitration lost
If the program triggers a start condition (by setting the IBCR10:MSS bit to "1") when no start condition has
been detected (IBSR0:BB bit = 0) and the SDA0 and SCL0 line pins are at the "L" level.
Figure 22.7-3 Timing Diagram with No Interrupt Generated with IBCR00:ALF = 1
400
SCL0 or SDA0 pin at "L" level
SCL0 pin
SDA0 pin
2
I C operation enabled (ICCR0:EN bit = 1)
Master mode set (IBCR10:MSS bit = 1)
Arbitration lost detection bit
(IBCR00:ALF bit = 1)
Bus busy (IBSR0:BB bit)
Interrupt (IBCR10:INT bit)
"L"
"L"
1
0
0