Fujitsu F2MC-8FX Hardware Manual page 227

Table 14.3-2 Functional Description of Each Bit of Watch Counter Status Register (WCSR)
Bit name
ISEL:
Watch counter start &
bit7
interrupt request enable
bit
WCFLG:
bit6 Interrupt request flag
bit
bit5
bit4
bit3 CTR5 to CTR0:
bit2 Counter read bits
bit1
bit0
• This bit activates the watch counter and selects whether to enable interrupts of the watch counter or
those of the watch prescaler.
When set to "0":The watch counter is cleared and stopped. Moreover, interrupt requests of the
watch counter are disabled, while interrupt requests of the watch prescaler are
enabled.
When set to "1":The interrupt request output of the watch counter is enabled and the counter starts
operation.
On the other hand, interrupt requests of the watch prescaler are disabled.
• Always disable interrupts of the watch prescaler before setting this bit to "1" to select interrupts of
the watch counter.
• The watch counter performs counting, using an asynchronous clock from the watch prescaler. For
this reason, an error of up to one count clock may occur at the beginning of a count cycle,
depending on the timing for setting ISEL bit to "1".
• This bit is set to "1" when the counter underflows.
• When this bit and the ISEL bit are both set to "1", a watch counter interrupt is generated.
• Writing "0" clears the bit.
• Writing "1" has no effect on the operation.
• "1" is always read in read-modify-write operation.
• These bits can read the counter value during counting. It should be noted that the correct counter
value may not be read if a read is attempted while the counter value is being changed. Therefore,
read the counter value twice to check if the same value is read on both occasions before using it.
• Write has no effect on the operation.
CHAPTER 14 WATCH COUNTER
Function
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