Fujitsu F2MC-8FX Hardware Manual page 386

2
CHAPTER 22 I C
2
I C Block Diagram
IBSR0
IBCR10
IBSR0
IBCR00
372
Figure 22.2-1 I
ICCR0
Clock divider 1
DMBP
5
EN
Clock selector 1
CS4
CS3
Clock divider 2
CS2
CS1
4 8
CS0
BB
Bus busy
Repeat start
RSC
Last bit
LRB
Transmit/receive
TRX
FBT
Arbitration lost detection circuit
BER
BEIE
INTE
INT
Start
SCC
Master
ACK enable
MSS
GC-ACK enable
DACKE
Address ACK enable
GACKE
INT timing select
Slave
AAS
GCA
General
call
AACKX
INTS
ALF
ALE
SPF
SPE
WUF
WUE
2
C Block Diagram
2
I C enable
6 7 8
22 38 98 128 256 512
Clock selector 2
Start/stop condition
detection circuit
Error
First byte
Transfer interrupt
End
Start/stop condition
generation circuit
IDDR0 register
Slave address
comparison circuit
IAAR0 register
Stop interrupt
Machine clock
Sync
Shift clock
generator
Shift clock edge
SCL I line
SDA line