CHAPTER 6 CLOCK CONTROLLER
Clock Mode State Transition Diagram
The clock modes available are: main clock mode, main PLL clock mode and subclock mode. The device
can switch between these modes according to the settings in the system clock control register (SYCC).
Figure 6.7-1 Clock Mode State Transition Diagram (Two-system Clock Product)
(2)
Subclock oscillation
stabilization wait time
64
Power on
Reset state
<1>
<2>
Main clock oscillation
stabilization wait time
Main clock mode
(4)
(3)
(1)
Main clock oscillation
stabilization wait time
(8)
(9)
Subclock mode
Reset occurs in each state.
(5)
Main PLL clock
oscillation stabiliza-
tion wait time
(6)
(7)
Main PLL
clock mode
Main clock/main PLL
clock oscillation
stabilization wait time