Fujitsu F2MC-8FX Hardware Manual page 361

Reception error in asynchronous clock mode (UART)
If any of the following three error flags (PER, FER, OVE) has been set, receive data is not transferred to
the UART/SIO serial input data register (RDR0) and the receive data register full (RDRF) bit is not set to
"1" either.
1. Parity error (PER)
The parity error (PER) bit is set to "1" if the parity bit in received serial data does not match the parity
polarity bit (TDP) when the parity control bit (PEN) contains "1".
2. Framing error (FER)
The framing error (FER) bit is set to "1" if "1" is not detected at the position of the first stop bit in serial
data received in the set character bit length (CBL) under parity control (PEN). Note that the stop bit is
not checked if it appears at the second bit or later.
3. Overrun error (OVE)
Upon completion of reception of serial data, the overrun error (OVE) bit is set to "1" if the reception of
the next data is performed before the previous receive data is read.
Each flag is set at the position of the first stop bit.
Figure 20.7-4 Setting Timing for Receiving Errors
UI D5
PER
OVE
FER
Reception
interrupt
D6 D7 P SP
CHAPTER 20 UART/SIO
SP
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