Fujitsu F2MC-8FX Hardware Manual page 71

Table 6.5-1 Functions of Bits in Oscillation Stabilization Wait Time Setting Register (WATR) (1 / 2)
Bit name
SWT3, SWT2,
bit7 SWT1, SWT0:
to Subclock oscillation
bit4 stabilization wait time
selection bits
Set the subclock oscillation stabilization wait time.
SWT3 SWT2 SWT1 SWT0
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
On single system clock product, the value of these bits is meaningless.
Number of cycles in the above table is for a minimum value. Add 1/F
above table for a maximum value.
Note: Do not update these bits during subclock oscillation stabilization wait time. You should
update them either with the subclock oscillation stability bit in the system clock control
register (SYCC:SRDY) set to "1" or in subclock mode. You can also update them while the
subclock is stopped with the subclock oscillation stop bit in the system clock control
register (SYCC:SUBS) set to "1" in main clock mode or main PLL clock mode.
CHAPTER 6 CLOCK CONTROLLER
Function
Number of
Subclock F
Cycles
15
15
(2 -2)/F
2 -2
14
14
(2 -2)/F
2 -2
13
13
(2 -2)/F
2 -2
12
12
(2 -2)/F
2 -2
11
11
(2 -2)/F
2 -2
10
10
(2 -2)/F
2 -2
9
9
(2 -2)/F
2 -2
8
8
(2 -2)/F
2 -2
7
7
(2 -2)/F
2 -2
6
6
(2 -2)/F
2 -2
5
5
(2 -2)/F
2 -2
4
4
(2 -2)/F
2 -2
3
3
(2 -2)/F
2 -2
2
2
(2 -2)/F
2 -2
1
1
(2 -2)/F
2 -2
1
1
(2 -2)/F
2 -2
= 32.768 kHz
CL
About
1.0 s
CL
About
0.5 s
CL
About
0.25 s
CL
About
0.125 s
CL
About
62.44 ms
CL
About
31.19 ms
CL
About
15.56 ms
CL
About
7.75 ms
CL
About
3.85 ms
CL
About
1.89 ms
CL
915.5 μs
About
CL
427.2 μs
About
CL
183.1 μs
About
CL
61.0 μs
About
CL
0.0 μs
CL
0.0 μs
CL
to the number of cycle in the
CL
57