Fujitsu F2MC-8FX Hardware Manual page 181

The counter of the timebase timer is also cleared and stops the operation if a reset occurs while the main
clock is still running after the main clock oscillation stabilization wait time has elapsed. The counter,
however, continues to operate during a reset if a count is required for the oscillation stabilization wait time.
Operating Examples of Timebase Timer
Figure 10.5-2 shows operating examples of operation under the following conditions:
1) When a power-on reset is generated
2) When entering the sleep mode during the operation of the interval timer function in the main clock
mode or main PLL clock mode
3) When entering the stop mode during the main clock mode or main PLL clock mode
4) When a request is issued to clear the counter
The same operation is performed when changing to the timebase timer mode as for when changing to the
sleep mode.
In the subclock mode, sub PLL clock mode, main clock mode and main PLL clock mode, the timer
operation is stopped during the stop mode, as the timebase timer is cleared and the main clock halts. Upon
recovering from the stop mode, the timebase timer is used to count the oscillation stabilization wait time.
Counter value
(count down)
3FFFFF
Count value detected in
WATR:MWT3, 2, 1, 0
Count value detected in
TBTC:TBC1, 0
000000
Oscillation
stabilization wait time
1) Power-on reset
TBIF bit
TBIE bit
2) SLP bit
(STBC register)
3) STP bit
(STBC register)
• When setting "11" to interval time select bits of timebase timer control register (TBTC:TBC1, 0) (2
• TBTC:TBC1,0 : Interval time select bits of timebase timer control register
• TBTC:TCLR
• TBTC:TBIF
• TBTC:TBIE
• STBC:SLP
• STBC:STP
• WATR:MWT
Figure 10.5-2 Operations of Timebase Timer
: Timebase timer initialization bit of timebase timer control register
: Timebase timer interrupt request flag bit of timebase timer control register
: Timebase timer interrupt request enable bit of timebase timer control register
: Sleep bit of standby control register
: Stop bit of standby control register
: Main clock oscillation stabilization wait time select bit of oscillation stabilization wait time setup register
Interval cycle
(TBTC:TBC1, 0 = 11)
Clear by transferring
to stop mode
4) Counter clear
(TBTC:TCLR = 1)
Clear in interrupt
Clear at interval
processing routine
setup
Sleep
Sleep cancelled by time-
base timer interrupt (TIRQ)
Stop cancelled by external interrupt
16
x 2/F
CHAPTER 10 TIMEBASE TIMER
Oscillation
stabilization wait time
Stop
)
CH
167