Fujitsu F2MC-8FX Hardware Manual page 367

F2mc-8fx 8-bit microcontroller

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Figure 20.7-11 Registers Used for Reception in Operation Mode 1

SCM10 (UART/SIO serial mode control register 1)

SCM20 (UART/SIO serial mode control register 2)

SSR0 (UART/SIO serial status and data register)

TDR0 (UART/SIO serial output data register)

RDR0 (UART/SIO serial input data register)

x : Unused bit

The reception depends on whether the serial clock has been set to external or internal clock.

When the reception operation enable bit (RXE) contains "1", serial data is received always at the rising

edge of the external clock signal.

The serial clock signal is outputted in accordance with transmission. Therefore, transmission must be

performed even when only performing reception. The following two procedures can be used.

• Set the transmission operation enable bit (TXE) to "1", then write transmit data to the UART/SIO serial

output data register to generate the serial clock signal and start reception.

CHAPTER 20 UART/SIO

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