Overview Of I 2 C - Fujitsu F2MC-8FX Hardware Manual

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CHAPTER 22 I C
22.1 Overview of I
2
The I C interface supports the I
provides the functions of transmission and reception in master and slave modes,
detection of arbitration lost, detection of slave address and general call address,
generation and detection of start and stop conditions, bus error detection, and MCU
standby wakeup.
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I C Functions
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The I C interface is a two-wire, bi-directional bus consisting of a serial data line (SDA) and serial clock
line (SCL). The devices connected to the bus via these two wires can exchange data, and each device can
operate as a sender or receiver in accordance with their respective functions based on the unique address
assigned to each device. Furthermore, the interface establishes a master/slave relationship between devices.
Also, the I
limit of 400 pF. The I
control protocol that prevent loss of data even if more than one master attempts to start a data transfer at the
same time.
The communication control protocol ensures that only one master is able to take control of the bus at a
time, even if multiple masters attempt to take control of the bus simultaneously, without messages being
lost or data being altered. Multi-master means that more than one master can attempt to take control of the
bus at the same time without causing messages to be lost.
Also, the I
Microcontroller
A
SDA
SCL
370
2
C
2
C bus specification published by Philips. The interface
2
C interface can connect multiple devices provided the bus capacitance does not exceed an upper
2
C interface is a true multi-master bus with collision detection and a communication
2
C interface includes a function to wake up the MCU from standby mode.
Figure 22.1-1 I
Gate array
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C Interface Configuration
LCD driver
A/D converter
Static RAM/
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E PROM
Microcontroller
B