Operating Description Of Pwm Timer Function (Variable-Cycle Mode) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 16 8/16-BIT COMPOSITE TIMER
16.11 Operating Description of PWM Timer Function (Variable-
cycle Mode)
This section describes the operations of the PWM timer function (variable-cycle mode)
for the 8/16-bit composite timer.
Operation of PWM Timer Function (Variable-cycle Mode)
The composite timer requires the settings shown in Figure 16.11-1 to serve as the PWM timer function
(variable-cycle mode).
Figure 16.11-1 Settings for PWM Timer Function (Variable-cycle Mode)
T00/01CR0
T00/01CR1
TMCR
T00DR
T01DR
In PWM timer function (variable-cycle mode), both timers 00 and 01 are used when the cycle is specified
by the 8/16-bit composite timer 01 data register (T01DR), and the "L" pulse width is specified by the 8/16-
bit composite timer 00 data register (T00DR), any cycle and duty PWM signal is generated from the timer
output bit (TO00).
For this function, the composite timer cannot serve as a 16-bit counter as the two 8-bit counters are used.
Enabling timer operation (by setting either T00CR1:STA = 1 or T01CR1:STA = 1) sets the mode bit
(TMCR0:MOD) to "0".
As the first cycle always begins with "L" pulse output, the timer initial value setting bit (T00CR1/
T01CR1:SO) is meaningless.
The interrupt flag (T00CR1/T01CR1:IF) is set when each 8-bit counter matches the value in the
corresponding 8/16-bit composite timer 00/01 data register (T00DR/T01DR).
The 8/16-bit composite timer 00/01 data register value is transferred to the temporary storage latch
(comparison data storage latch) in the comparator either when the counter starts counting or when a
comparison match with each counter value is detected.
"H" is not outputted when the "L" pulse width setting value is greater than the cycle setting value.
The count clock must be selected for both of timers 00 and 01. Selecting different count clocks, however, is
prohibited.
When the timer stops operation, the timer output bit (TMCR0:TO0) holds the last output value.
If the 8/16-bit composite timer 00/01 data register is written over during operation, the written data will be
effective from the cycle immediately after the detection of a synchronous match.
264
bit7 bit6 bit5
IFE C2 C1
STA HO IE
1
TO1 TO0 IIS
×
Sets "L" pulse width (compare value)
Sets the cycle of PWM waveform (compare value)
: Used bit
×: Unused bit
1: Set "1"
bit4 bit3 bit2
C0 F3 F2
0 1
IR BF IF
× ×
MOD FE11 FE10
×
bit1 bit0
F1 F0
0 0
SO OE
× ×
FE01 FE00