Fujitsu F2MC-8FX Hardware Manual page 138

CHAPTER 9 I/O PORT
Operation in stop mode and watch mode
• If the pin state specification bit in the standby control register (STBC:SPL) is set to "1" when the device
switches to stop or watch mode, the pin is set forcibly to the high-impedance state regardless of the
DDR value. Note that the input is locked to "L" and blocked in order to prevent leaks due to freed input.
However, if the peripheral function input (SCL0, SDA0) is enabled, the input is enabled and not
blocked.
• If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O and the
output is maintained.
Operation of the input level selection register
• The input levels of P50 and P51 are determined by the bit3/bit4 of ILSR and bit4 of ILSR2.When bit3/
bit4 of ILSR is "1", ignoring the bit1 of ILSR2's value,P50/P51 should be CMOS input level.When bit3/
bit4 of ILSR is "0", if bit3 of ILSR2 is "0",P50 should be hysteresis input level, otherwise P50 should be
automotive input level. if bit4 of ILSR2 is "0",P51 should be hysteresis input level, otherwise P51
should be automotive input level.
• Make sure that the input level for P51 and P50 is changed during the peripheral function (I
Table 9.5-4 shows the pin states of the port.
Table 9.5-4 Pin State of Port 5
Normal operation
Operating Sleep
state Stop (SPL=0)
Watch (SPL=0)
I/O port/
Pin state
peripheral function I/O
SPL: Pin state specification bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled; it requires the pull-up or pull-down operation, or preventing
leaks by external inputs. Same as other ports when used as an output port.
124
Stop (SPL=1)
Watch (SPL=1)
Hi-Z
(the pull-up setting is enabled)
Input cutoff
2
C0) stopped.
At reset
Hi-Z
Input enabled*
(Not functional)