A/D Data Registers (Addh, Addl) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 23 10-BIT A/D CONVERTER
23.4.3

A/D Data Registers (ADDH, ADDL)

The A/D data registers (ADDH, ADDL) contain the results of 10-bit A/D conversion.
The high-order two bits of 10-bit data correspond to the ADDH register; the low-order
eight bits correspond to the ADDL register.
A/D Data Registers (ADDH, ADDL)
ADDH
Address
006E
H
ADDL
Address
006F
H
R/WX : Read only (Readable, writing has no effect on operation)
R0/WX : Undefined bit (Read value is "0", writing has no effect on operation)
The upper two bits of 10-bit A/D data correspond to bits 1 and 0 in the ADDH register; the lower eight bits
correspond to bits 7 to 0 in the ADDL register.
Set the AD8 bit in the ADC2 register to "1" to select 8-bit precision mode, so that 8-bit data can be read
from the ADDL register.
These registers are read-only. Writing either is meaningless.
During 8-bit conversion, SAR8 and SAR9 hold "0".
A/D conversion functions
When A/D conversion is started, the results of conversion are finalized and stored in these registers after
the conversion time according to the register settings has passed. After A/D conversion finishes, therefore,
read the A/D data registers (conversion results), write "0" to the ADI bit (bit 3) in the ADC1 register before
the next A/D conversion terminates, then after A/D conversion finishes, clear the flag. During A/D
conversion, the registers contain the values resulting from the last conversion performed.
422
Figure 23.4-4 A/D Data Registers (ADDH, ADDL)
bit7 bit6 bit5
- - -
R0/WX R0/WX R0/WX R0/WX
bit15 bit14 bit13
SAR7 SAR6 SAR5
R/WX R/WX R/WX
bit4 bit3 bit2
SAR9
- - -
R0/WX R0/WX R/WX
bit12 bit11 bit10
SAR4 SAR3 SAR2 SAR1
R/WX R/WX R/WX R/WX
bit1 bit0 Initial value
SAR8 00000000
R/WX
bit9 bit8 Initial value
00000000
SAR0
R/WX
B
B