Fujitsu F2MC-8FX Hardware Manual page 351

Table 20.5-2 Functional Description of Each Bit of UART/SIO Serial Mode Control Register 2 (SMC20)
Bit name
SCKE:
bit7 Serial clock output
enable bit
TXOE:
bit6 Serial data output
enable bit
RERC:
bit5 Reception error flag
clear bit
RXE:
bit4 Reception operation
enable bit
TXE:
bit3 Transmission operation
enable bit
RIE:
bit2 Reception interrupt
enable bit
TCIE:
Transmission
bit1
completion interrupt
enable bit
TEIE:
Transmission data
bit0
register empty interrupt
enable bit
This bit controls the input/output of the serial clock (UCK) pin in clock synchronous mode.
Setting the bit to "0" allows the pin to be used as a general-purpose port.
Setting the bit to "1" enables clock output.
Note: When CKS is "1", the internal clock signal is not outputted even with this bit set to "1".
If this bit is set to "1" with SCM1:MD set to 0 (asynchronous mode), the output from the
port will always be "H".
This bit controls the output of the serial data (UO pin).
Setting the bit to "0" allows the pin to be used as a general-purpose port.
Setting the bit to "1" enables serial data output.
Setting the bit to "0" clears the SSR register error flags (PER, OVE, FER).
Setting the bit to "1" clears the reception error flag.
• Reading this bit always returns "1".
Setting the bit to "0" disables the reception of serial data.
Setting the bit to "1" enables the reception of serial data.
• If this bit is set to "0" during reception, the reception operation will be immediately disabled and
initialization will be performed. The data received up to that point will not be transferred to the
UART/SIO serial input data register.
Note: Setting this bit to "0" initializes reception operation. It has no effect on the interrupt flags
(PER, OVE, FRE, RDRF).
Setting the bit to "0" disables the transmission of serial data.
Setting the bit to "1" enables the transmission of serial data.
• If this bit is set to "0" during transmission, the transmission operation will be immediately disabled
and initialization will be performed. The transmission completion flag (TCPL) will be set to "1"
and the transmission data register empty (TDRE) bit will also be set to "1".
Setting the bit to "0" disables reception interrupt.
Setting the bit to "1" enables reception interrupt.
• A reception interrupt occurs immediately after either the receive data register full (RDRF) bit or an
error flag (PER, OVE, FER, or RDRF) is set to "1" with this bit set to "1" (enabled).
Setting the bit to "0" disables interrupts by the transmission completion flag.
Setting the bit to "1" enables interrupts by the transmission completion flag.
• A transmission interrupt occurs immediately after the transmission completion flag (TCPL) bit is
set to "1" with this bit set to "1" (enabled).
Setting the bit to "0" disables interrupts by the transmission data register empty.
Setting the bit to "1" enables interrupts by the transmission data register empty.
• A transmission interrupt occurs immediately after the transmission data register empty (TDRE) bit
is set to "1" with this bit set to "1" (enabled).
CHAPTER 20 UART/SIO
Function
337