Configuration Of Prescaler - Fujitsu F2MC-8FX Hardware Manual

6.11

Configuration of Prescaler

Figure 6.11-1 is a block diagram of the prescaler.
Prescaler Block Diagram
MCLK (machine clock)
7
2 /F
CH
From
timebase
timer
8
2 /F
CH
MCLK: Machine clock (internal operating frequency)
• 5-bit counter
The machine clock (MCLK) is counted by a 5-bit counter and the count value is output to the output
control circuit.
• Output control circuit
Based on the 5-bit counter value, this circuit supplies clocks generated by frequency-dividing the
machine clock (MCLK) by 2, 4, 8, 16, or 32 to individual peripheral resources. The circuit also buffers
the clock from the timebase timer (2
Input Clock
The prescaler uses the machine clock or the clock output from the timebase timer as the input clock.
Output Clock
The prescaler supplies clocks to the 8/10-bit composite timer, 16-bit PPG timer, UART/SIO dedicated baud
rate generator, and 10-bit A/D converter.
Figure 6.11-1 Prescaler Block Diagram
Prescaler
Counter value
5-bit
counter
7
/F and 2
CH
CHAPTER 6 CLOCK CONTROLLER
Output
control circuit
8
/F ) and supplies it to the peripheral resources.
CH
2/MCLK
4/MCLK
Count
8/MCLK
clock
source
16/MCLK
To
32/MCLK
individual
peripheral
resources
7
2 /F
CH
8
2 /F
CH
79