Fujitsu F2MC-8FX Hardware Manual page 360

CHAPTER 20 UART/SIO
Receiving operation in asynchronous clock mode (UART)
Use UART/SIO serial mode control register 1 (SMC10) to select the serial data direction (endian), parity/
non-parity, parity polarity, stop bit length, character bit length, and clock.
Reception remains performed as long as the reception operation enable bit (RXE) contains "1".
Upon detection of a start bit in receive data with the reception operation enable bit (RXE) set to "1", one
frame of data is received according to the data format set in UART/SIO serial control register 1 (SMC10).
When the reception of one frame of data has been completed, the received data is transferred to the UART/
SIO serial input data register (RDR0) and the next frame of serial data can be received.
When the UART/SIO serial input data register (RDR0) stores data, the receive data register full (RDRF) bit
is set to "1".
A reception interrupt occurs the moment the receive data register full (RDRF) bit is set to "1" when the
reception interrupt enable bit (RIE) contains "1".
Received data is read from the UART/SIO serial input data register (RDR0) after each error flag (PER,
OVE, FER) in the UART/SIO serial status and data register is checked.
When received data is read from the UART/SIO serial input data register (RDR0), the receive data register
full (RDRF) bit is cleared to "0".
Note that modifying UART/SIO serial mode control register 1 (SMC10) during reception may result in
unpredictable operation.
If the RXE bit is set to "0" during reception, the reception is immediately disabled and initialization will be
performed. The data received up to that point will not be transferred to the serial input data register.
Figure 20.7-3 Receiving Operation in Asynchronous Clock Mode
RXE
UI
RDR0
read
RDRF
346
St D0 D1 D2 D3 D4 D5 D6 D7 Sp Sp St D0 D1 D2