Watch Counter Control Register (Wcsr) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 14 WATCH COUNTER
14.3.2

Watch Counter Control Register (WCSR)

The watch counter control register (WCSR) is used to control the operation and
interrupts of the watch counter. It can also read the count value.
Watch Counter Control Register (WCSR)
bit7
Address
ISEL
0070
H
R/W R(RM1)/W R/WX R/WX R/WX R/WX
ISEL
0
1
R/W
R/WX
R(RM1),W
212
Figure 14.3-3 Watch Counter Control Register (WCSR)
bit6 bit5 bit4 bit3
CTR5 CTR4 CTR3
WCFLG
WCFLG
0
No interrupt request generated
1
An interrupt request generated
Watch counter start & interrupt enable bit
Stops watch counter and disables interrupt request of watch counter (Enables interrupt request of watch prescaler)
Activates watch counter and enables interrupt request of watch counter (Disables interrupt request of watch prescaler)
: Initial value
: Readable/writable (Read value is the same as write value)
: Read only (Readable, writting has no effect on operation)
: Readable/writable (Read value is different from write value, "1" is read by read-modfy-write instruction)
bit2 bit1 bit0 Initial value
CTR2 CTR1 CTR0 00000000
R/WX R/WX
CTR5 to
These bits can read the counter value.
CTR0
Interrupt request flag bit
Read
B
Write
Clears this bit
No change, no effect on operation