Fujitsu F2MC-8FX Hardware Manual page 505

F2mc-8fx 8-bit microcontroller
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Table 27.3-1 Functional Description of Each Bit of real time clock control register upper
Bit name
MOS: Month alarm
Bit7
interrupt request
signal
DS: Day alarm
Bit6
interrupt request
signal
HS: Hour alarm
Bit5
interrupt request
signal
MS: Minute alarm
Bit4
interrupt request
signal
MOC: Month
Bit3
compare bit
DC: Day compare
Bit2
bit
HC: Hour compare
Bit1
bit
• When MOC bit set to one, the month comparison will be done between the compare
register and the counter. When they match, MOS will be set to one. An interrupt request
may be sent to the CPU, which depends on the settings of compare bits and
RTCCRL:INTS
• Writing "0" clears this bit.
• Writing "1" has no effect on this bit and does not alter the bit value.
• This bit is cleared by reset.
• in read-modify-write operation, "1" is always read.
• When DC bit set to one, the day comparison will be done between the compare register
and the counter. When they match, DS will be set to one. An interrupt request may be
sent to the CPU, which depends on the settings of compare bits and RTCCRL:INTS.
• Writing "0" clears this bit.
• Writing "1" has no effect on this bit and does not alter the bit value.
• This bit is cleared by reset.
• In read-modify-write operation, "1" is always read.
• When HC bit set to one, the day comparison will be done between the compare register
and the counter. When they match, HS will be set to one. An interrupt request may be
sent to the CPU, which depends on the settings of compare bits and RTCCRL:INTS.
• Writing "0" clears this bit.
• Writing "1" has no effect on this bit and does not alter the bit value.
• This bit is cleared by reset.
• In read-modify-write operation, "1" is always read.
• When MC bit set to one, the day comparison will be done between the compare register
and the counter. When they match, MS will be set to one. An interrupt request may be
sent to the CPU, which depends on the settings of compare bits and RTCCRL:INTS.
• Writing "0" clears this bit.
• Writing "1" has no effect on this bit and does not alter the bit value.
• This bit is cleared by reset.
• In read-modify-write operation, "1" is always read.
• When this bit set to "1" and RTCCRL:INTS set to "0", the month compare register is
being continuously compared with the month counter for detecting alarm condition. If
there is match, an interrupt request will be sent to the CPU.
• When this bit set to "1" and RTCCRL:INTS set to "1", an interrupt will be sent according
to the table 1.5-2.
• When this bit is set to zero, it disables the month comparison.
• When this bit set to "1" and RTCCRL:INTS set to "0", the day compare register is being
continuously compared with the month counter for detecting alarm condition. If there is
match, an interrupt request will be sent to the CPU.
• When this bit set to "1" and RTCCRL:INTS set to "1", an interrupt will be sent according
to the table 1.5-2.
• When this bit is set to zero, it disables the day comparison.
• When this bit set to "1" and RTCCRL:INTS set to "0", the hour compare register is being
continuously compared with the hour counter for detecting alarm condition. If there is
match, an interrupt request will be sent to the CPU.
• When this bit set to "1" and RTCCRL:INTS set to "1", an interrupt will be sent according
to the table 1.5-2.
• When this bit is set to zero, it disables the hour comparison.
CHAPTER 27 REAL TIME CLOCK
Function
491

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