Explanation Of Watch Counter Operations And Setup Procedure Example - Fujitsu F2MC-8FX Hardware Manual

14.5 Explanation of Watch Counter Operations and Setup
Procedure Example
The watch counter counts down for the number of times specified in the count value by
RCTR5 to RCTR0 bits, using the count clock selected by CS1 and CS0 bits, when the
ISEL bit is set to "1". Once the counter underflows, WCFLG bit of the WCSR register is
set to "1", generating an interrupt.
Setup Procedure of Watch Counter
The setup procedure of the watch counter is described below.
(1) Select the count clock (CS1 and CS0 bits) and set the counter reload value (RCTR5 to RCTR0 bits).
(2) Set the ISEL bit of the WCSR register to "1" to start a down count and enable interrupts. Also disable
interrupts of the watch prescaler.
The watch counter performs counting by using a divided clock (asynchronous) from the watch
prescaler. An error of up to one count clock may occur at the beginning of a count cycle, depending on
the timing for setting the ISEL bit to "1".
(3) When the counter underflows, the WCFLG bit of the WCSR register is set to "1", generating an
interrupt.
(4) Write "0" to the WCFLG bit to clear it.
(5) If RCTR5 to RCTR0 bits are modified during counting, the reload value will be updated during a
reload after the counter is set to "1".
(6) When writing "0" to the ISEL bit, the counter becomes "0" and stops operation.
ISEL
Count clock
CS1,0
RCTR5 to 0
CTR5 to 0
WCFLG
Figure 14.5-1 Descriptive Diagram of Watch Counter Operation
(2)
(1)
7
0 7 6 5 4 3 2 1 9 8 7 6 5 4
CHAPTER 14 WATCH COUNTER
"1,1"
9
(5)
(3) (4)
(6)
0
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