Explanation Of Timebase Timer Operations And Setup Procedure Example - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 10 TIMEBASE TIMER
10.5 Explanation of Timebase Timer Operations and Setup
Procedure Example
This section describes the operations of the interval timer function of the timebase
timer.
Operations of Timebase Timer
The counter of the timebase timer is initialized to "3FFFFF" after a reset and starts counting while being
synchronized with the main clock divided by two.
The timebase timer continues to count down as long as the main clock is oscillating. Once the main clock
halts, the counter stops counting and is initialized to "3FFFFF".
The settings shown in Figure 10.5-1 are required to use the interval timer function.
Address
000A
H
: Bit used
1: Set to 1
0: Set to 0
When the timebase timer initialization bit in the timebase timer control register (TBTC:TCLR) is set to "1",
the counter of the timebase timer is initialized to "3FFFFF" and continues to count down. When the
selected interval time has elapsed, the timebase timer interrupt request flag bit of the timebase timer control
register (TBTC:TBIF) becomes "1". In other words, an interrupt request is generated at each interval time
selected, based on the time when the counter was last cleared.
Clearing Timebase Timer
If the timebase timer is cleared when the output of the timebase timer is used in other peripheral functions,
this will affect the operation by changing the count time or in other manners.
When clearing the counter by using the timebase timer initialization bit (TBTC:TCLR), perform setup so
that this does not have unexpected effects on other peripheral functions.
When the output of the timebase timer is selected as the count clock for the watchdog timer, clearing the
timebase timer also clears the watchdog timer.
The timebase timer is cleared not only by the timebase timer initialization bit (TBTC:TCLR), but also when
the main clock is stopped and a count is required for the oscillation stabilization wait time. More
specifically, the timebase timer is cleared in the following situations:
• When moving from the main clock mode or main PLL clock mode to the stop mode
• When moving from the main clock mode or main PLL clock mode to the subclock mode or sub PLL
clock mode
• At power on
• At low-voltage detection reset
166
Figure 10.5-1 Settings of Interval Timer Function
bit7 bit6
TBTC TBIF TBIE
0 1
bit5 bit4 bit3 bit2
TBC1
- - -
bit1 bit0
TBC0 TCLR
0