Interrupt Processing Time - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 8 INTERRUPTS
8.1.4

Interrupt Processing Time

The time between an interrupt request being generated and control being passed to the
interrupt processing routine is equal to the sum of the time until the currently executing
instruction completes and the interrupt handling time (time required to initiate interrupt
processing). This time consists of a maximum of 26 machine clock cycles.
Interrupt Processing Time
The interrupt request sampling wait time and interrupt handling time intervene between the occurrence and
acceptance of an interrupt request and the execution of the relevant interrupt service routine.
Interrupt request sampling wait time
Whether an interrupt request has occurred is determined through the sampling of the interrupt request
during the last cycle of each instruction. The CPU cannot therefore recognize interrupt requests during the
execution of each instruction. The maximum length of this delay occurs if the interrupt request is generated
immediately after the DIVU instruction requiring the longest instruction cycle (17 machine clock cycles)
starts executing.
Interrupt handling time
After receiving an interrupt, the CPU requires 9 machine clock cycles to perform the following interrupt
processing setup:
• Saves the program counter (PC) and program status (PS) values.
• Sets the PC to the start address (interrupt vector) of interrupt service routine.
• Updates the interrupt level bits (PS:CCR:IL1, IL0) in the program status (PS) register.
CPU operation
Interrupt wait time
When an interrupt request is generated immediately after the beginning of execution of the DIVU instruction
requiring the longest execution cycle (17 machine clock cycles), it takes an interrupt processing time of
17+9=26 machine clock cycles.However, if you do not use the DIVU or MULU instructions in your pro-
gram, the
The machine clock changes depending on the clock mode and main clock speed switching (gear function).
For details, refer to CHAPTER 6 CLOCK CONTROLLER.
98
Figure 8.1-4 Interrupt Processing Time
Normal instruction execution
Interrupt request
sampling wait time
Interrupt request generated
: Last instruction cycle in which the instruction request is sampled
maximum interrupt processing time becomes
Interrupt handling Interrupt service routine
Interrupt handling time
(9 machine clock cycles)
7 + 9=16
machine clock cycles.