Fujitsu F2MC-8FX Hardware Manual page 143

Operation in stop mode and watch mode
• If the pin state specification bit in the standby control register (STBC:SPL) is set to "1" when the device
switches to stop or watch mode, the pin is set forcibly to the high-impedance state regardless of the
DDR value. Note that the input is locked to "L" and blocked in order to prevent leaks due to freed input.
If the pin state specification bit is "0", the state remains in port I/O or peripheral function I/O and the
output is maintained.
Operation as a LCDC segment output
• Set the DDR register bit, which is corresponding to the LCDC segment output pin, to "0".
• For other peripheral functions sharing pins, disable its output.
• Select the common/segment pin in LCDC enable registers (LCDCE1 to 6), and then set the port input
control bit (PICTL) in LCDC enable register (LCDCE1) to "1".
Operation of the input level selection register
• Writing "1" to the bit5 of ILSR2 changes Port 6 from the hysteresis input level to the automotive input
level. When the bit5 of ILSR2 is "0", it should be the hysteresis input level.
Table 9.6-4 shows the pin states of the port.
Table 9.6-4 Pin State of Port 6
Normal operation
Operating Sleep
state Stop (SPL=0)
Watch (SPL=0)
I/O port/
Pin state
peripheral function I/O
SPL: Pin state specification bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means that the input function is enabled; it requires the pull-up or pull-down operation, or preventing
leaks by external inputs. Same as other ports when used as an output port.
Stop (SPL=1)
Watch (SPL=1)
Hi-Z
Input cutoff
CHAPTER 9 I/O PORT
At reset
Hi-Z
Input enabled* (Not functional)
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