Data Polling Flag (Dq7) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 28 256-KBIT FLASH MEMORY
28.5.1

Data Polling Flag (DQ7)

The data polling flag (DQ7) is a hardware sequence flag used to indicate that the
automatic algorithm is being executing or has been completed using the data polling
function.
Data Polling Flag (DQ7)
Table 28.5-3 and Table 28.5-4 show the state transition of the data polling flag.
Table 28.5-3 State Transition of Data Polling Flag (During Normal Operation)
Operating state
Table 28.5-4 State Transition of Data Polling Flag (During Abnormal Operation)
At programming
When read access takes place during execution of the automatic write algorithm, the flash memory outputs
the inverted value of bit 7 in the last data written to DQ7.
If read access takes place on completion of the automatic write algorithm, the flash memory outputs bit 7 of
the value read from the read-accessed address to DQ7.
At chip erasing
When read access is made to the sector currently being erased during execution of the chip erase algorithm,
bit 7 of flash memory outputs "0". Bit 7 of flash memory outputs "1" upon completion of chip erasing.
Note:
Once the automatic algorithm has been started, read access to the specified address is ignored.
Data reading is allowed after the data polling flag (DQ7) is set to "1". Data reading after the end of
the automatic algorithm should be performed following read access made to confirm the completion
of data polling.
530
Programming → Programming completed
DQ7
Operating state
DQ7
DQ7 → DATA: 7
Programming
DQ7
Chip erasing → Erasing completed
01
Chip erasing
0