Interrupt Level Setting Registers (Ilr0 To Ilr5) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 8 INTERRUPTS
8.1.1

Interrupt Level Setting Registers (ILR0 to ILR5)

The interrupt level setting registers (ILR0 to ILR5) contain 24 pairs of bits assigned for
the interrupt requests from different peripheral resources. Each pair of bits (interrupt
level setting bits as two-bit data) sets each interrupt level.
Configuration of Interrupt Level Setting Registers (ILR0 to ILR5)
Register Address
ILR0 00079
ILR1 0007A
ILR2 0007B
ILR3 0007C
ILR4 0007D
ILR5 0007E
The interrupt level setting registers assign each pair of bits for a different interrupt request. The values of
interrupt level setting bits in these registers specify interrupt service priorities (interrupt levels 0 to 3).
The interrupt level setting bits are compared with the interrupt level bits in the condition code register
(CCR: IL1, IL0).
When interrupt level 3 is set for an interrupt request, the CPU ignores the interrupt request.
Table 8.1-2 shows the relationships between interrupt level setting bits and interrupt levels.
Table 8.1-2 Relationships Between Interrupt Level Setting Bits and Interrupt Levels
LXX
0
0
1
1
XX:0 to 23 Corresponding interrupt number
During execution of a main program, usually, the interrupt level bits in the condition code register (CCR:
IL1, IL0) contain "11
94
Figure 8.1-1 Configuration of Interrupt Level Setting Registers
bit7 bit6 bit5
L03 [1:0] L02
H
L07 [1:0] L06
H
L11 [1:0] L10
H
L15 [1:0] L14
H
L19 [1:0] L18
H
L23 [1:0] L22
H
Requested Interrupt
LXX
Level
0
1
0
1
".
B
bit4 bit3 bit2
[1:0] L01 [1:0]
[1:0] L05 [1:0]
[1:0] L09 [1:0]
[1:0] L13 [1:0]
[1:0] L17 [1:0]
[1:0] L21 [1:0]
0
1
2
3
bit1 bit0 Initial value
L00 [1:0] R/W 11111111
L04 [1:0] R/W 11111111
L08 [1:0] R/W 11111111
L12 [1:0] R/W 11111111
L16 [1:0] R/W 11111111
L20 [1:0] R/W 11111111
Priority
Highest
Lowest (No interrupt accepted)
B
B
B
B
B
B