Fujitsu F2MC-8FX Hardware Manual page 297

16-bit PPG duty setting buffer register (upper): PDUTH
Address bit15
0FAE PDUTH0 DU15
H
0FB4 PDUTH1 R/W
H
0FBA PDUTH2
H
0FA8 PDUTH3
H
0F2E PDUTH4
H
0F34 PDUTH5
H
0F3A PDUTH6
H
0F28 PDUTH7
H
16-bit PPG duty setting buffer register (lower): PDUTL
Address bit7
0FAF PDUTL0 DU07
H
0FB5 PDUTL1 R/W
H
0FBB PDUTL2
H
0FA9 PDUTL3
H
0F2F PDUTL4
H
0F35 PDUTL5
H
0F3B PDUTL6
H
0F29 PDUTL7
H
16-bit PPG status control register (upper): PCNTH
Address 15
0042 PCNTH0 CNTE STRG MDSE RTRG CKS2
H
0044 PCNTH1 R/W
H
0046 PCNTH2
H
0050 PCNTH3
H
003A PCNTH4
H
003C PCNTH5
H
003E PCNTH6
H
0040 PCNTH7
H
16-bit PPG status control register (lower): PCNTL
Address 7
0043 PCNTL0 EGS1
H
0045 PCNTL1 R/W
H
0047 PCNTL2
H
0051 PCNTL3
H
003B PCNTL4
H
003D PCNTL5
H
003F PCNTL6
H
0041 PCNTL7
H
R/W: Readable/writable (Read value is the same as write value)
R/WX: Read only (Readable, writing has no effect on operation)
R(RM1), W: Readable/writable (Read value is different from write value, "1" is read by read-modify-
write instruction)
The following sections describe only the 16-bit PPG timer in ch.0.
The other channels are the same as it.
bit14 bit13 bit12
DU14 DU13 DU12 DU11
R/W R/W R/W
bit6 bit5 bit4
DU06 DU05 DU04 DU03
R/W R/W R/W
14 13 12
R0/W R/W R/W
6 5 4
EGS0 IREN IRQF
R/W R/W
R(RM1),W
CHAPTER 17 16-BIT PPG TIMER
bit11 bit10 bit9
DU10 DU09 DU08
R/W R/W R/W
bit3 bit2 bit1
DU02 DU01 DU01
R/W R/W R/W
11 10 9
CKS1 CKS0 PGMS
R/W R/W R/W
3 2 1
IRS1 IRS0 POEN OSEL
R/W R/W R/W
(Continued)
bit8 Initial value
11111111
B
R/W
bit0 Initial value
11111111
B
R/W
8 Initial value
00000000
B
R/W
0 Initial value
00000000
B
R/W
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